As the feature sizes of microelectronic assemblies (e.g., integrated circuits) continue to get smaller, manufacturing challenges become more apparent. For example, as the vias or interconnects, often made of copper, formed through interlayer dielectrics (ILDs) shrink in size with less distance separating adjacent vias, it becomes more difficult to form barrier layers within the via trenches which adequately prevent the copper (or other conductive material) from diffusing into the dielectric material, and possibly affecting circuit performance.
In recent years, tantalum nitride has been used with some success. However, as the thickness of the tantalum nitride is reduced to levels suitable for next generation devices (e.g., 1 nm), it often allows for an undesirable amount of copper diffusion, particular under relatively high temperatures (e.g., 350° C. and higher). Additionally, at such thicknesses, the degree of nucleation homogeneity, as well as compositional uniformity and control, becomes very demanding, requiring advanced atomic layer deposition (ALD) techniques and precursor chemistry.